ADUC7061BCPZ32 ARM Microcontrollers MCU DUAL 24BIT AFE et ARM 7 IC .
Product Description
Productum attributum | Precium attributum |
Fabrica: | Analoga Fabrica Inc. |
Product Category: | ARM Microcontrollers - MCU |
RoHS: | Singula |
Series: | ADUC7061 |
Adscendens Style: | SMD/SMT |
Sarcina / Case: | LFCSP-32 |
Core: | ARM7TDMI |
Programma Memoria Location: | 32 kB |
Data Bus Latitudo: | 32 bit/16 bit |
ADC Consilium: | 24 bit |
Maximum Horologium Frequency: | 10.24 MHz |
Numerus I / Os: | 8 I/O* |
Data Ram Size: | 4 kB |
Supple intentione - Min: | 2.375 V |
Supple intentione - Max: | 2.625 V |
Minimum Operating Temperature: | - 40 C |
Maximum Operating Temperature: | + 125 C |
Packaging: | Tray |
Notam: | Analog Devices |
Height: | 0.83 mm |
Interface Type: | JTAG |
Longitudo; | 5 mm |
Humor Sensitivus: | Ita |
Numerus ADC canales: | 10 Channel |
Numerus Timers / Calculis: | 4 Timer |
Processus Series: | ARM7 |
Product Type: | ARM Microcontrollers - MCU |
Programma Memoria Type: | Flash |
Factory Pack Quantity: | 1 |
Subcategoria: | Microcontrollers - MCU |
Latitudo: | 5 mm |
Unitas pondus: | 0.03802 oz |
♠ Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI
Series ADuC7060/ADuC7061 plene integrantur, 8 kSPS, 24-bit rationum acquisitionum systematum incorporatio magni canalis perficiendi sigma-delta (Σ-Δ) convertentium analog-ad-digitalium (ADCs), 16-bit/ 32-bit ARM7TDMI® MCU , et Mico/EE memoria in uno chip.
ADCs ex prima ADC constant cum duobus iugis differentialibus vel quattuor canalibus simplicibus finitis et auxiliaribus ADC usque ad septem canales.ADCs agunt in uno-finito vel differentiali initus modus.Unius canalis buffered intentionis output DAC in chip est praesto.DAC output range programmabilis est ad unum ex quattuor iugis intentionis.
Adinventiones agunt de chip oscillatore et PLL generantes internum altum frequentiam horologii usque ad 10.24 MHz.Core microcontroller est ARM7TDMI, 16-bit/32 frenum RISC apparatus offerens usque ad 10 MIPS apicem effectus;4 kB SRAM et 32 kB Flash/EE memoriae non volatilis praebentur in chip.ARM7TDMI nucleus omnes memoriam et tabulas ut unum linearem aciem inspicit.
In ADuC7060/ADuC7061 quattuor timers continet.Timer1 vigilator est timor cum facultate partam ex modo virtutis salutaris afferendi.Timer2 configurable as a watchdog timer.A 16-bit PWM cum sex canalibus output providetur.In ADuC7060/ ADuC7061 interregem moderatorem provectum continet.Vectored moderatorem interpellandi (VIC) permittit ut omnes interrumpentes gradu prioritatis assignandi sint.Sustinet etiam obloquitur nidificatum ad gradum maximum octo per IRQ et FIQ.Cum IRQ et FIQ fontes interrumpunt inter se componuntur, summa graduum 16 frondium interrumpentium sustentatur.In-chip officinas firmware subsidia in-circuitu Vide download per UART Vide portus interfacies et aemulatio nonintrusiva per interfaciem JTAG.Partes agunt ab 2.375 V ad 2.625 V supra 40°C ad +125°C per industriae temperaturam.
Analog initus / output
Dual (24-bit) ADCs
Una finita et differentialis inputs
Programmabilis ADC output rate (4 Hz ad 8 kHz)
Programmabiles digitales Filtra
Inaedificata ratio calibratiis
Humilis modus operatio virtutis
Primaria (24-bit) ADC alveum
II differentiae binae vel IV una-finivit channels
PGA (1 ad 512) input scaena
± 2.34 mV ad ±1.2 V
30 nV rms noise
Auxilia (24-bit) ADC: 4 paria differentialia vel 7 canales iunctae
On-chip accurate reference (± 10 ppm/°C)
Excitatio sensoris programmabilis fontes vena
200 µA ad 2 mA range fons currentis
Singula 14-bit voltage output DAC
Microcontroller
ARM7TDMI nucleus, 16-/32-bit architectura RISC
JTAG portum subsidia codice download et debug
Plures clocking optiones
Memoria
32 kB (16 kB 16) Mico / EE memoria, inter 2 kB nucleos
4 kB (1 kB 32) SRAM
Tools
In circuitu download, JTAG substructio debug
Minimum sumptus, QuickStart™ evolutionis systema
Communications interfaces
SPI interface (5 Mbps)
IV-byte recipere et transmittere FIFOs
UART Vide I/O et
2C (dominus/servus)
De-chip peripherals
4× generalis consilii (captis) timers comprehendo
Expergiscimini timer
Watchdog timer
Vectored adjicias controller pro FIQ et IRQ
VIII prioritatem gradus inter se adjicias genus
Interpellare in margine vel gradu externa clavum inputs
16-bit, 6-alveum PWM
General-proposito initibus / outputs
Ad 14 GPIO fibulae plene 3.3 V obsequentes
Potestas
AVDD/DVDD certa pro 2.5 V (± 5%)
Modus activus: 2.74 mA (@ 640 kHz, ADC0 activum)
10 mA (@ MHz 10.24, utrumque ADCs activum);
Packages and temperatus range
Plene certa pro -40 ° C ad CXXV ° C operatio
32-plumbum LFCSP (5 mm × 5 mm);
48 cerussae LFCSP et LQFP
Derivationes
32-plumbum LFCSP (ADuC7061)
48, cerussam LQFP et 48 cerussam LFCSP (ADuC7060);
Industriae automation et processus imperium
Intelligens, subtilis systemata sentiendi, 4 mA ad 20 mA .
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