FS32K116LIT0VFMR S32K116 Brachium Cortex-M0+, 48 MHz, 128 Kb Mico, ISELED, FlexIO, QFN32 – S32K MCUs ad propositum generale

• Operating characteres
- Voltage range: 2.7 V ad 5.5 V
- Ambiens temperatus range: -40 °C ad CV °C pro HSRUN modus, -40 °C ad CL °C pro CURSUS modus
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
- subsidia ad frequentiam MHz 112 (HSRUN modus) cum 1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and Thumb®-2 ISA
- Integrated signum Processus Digital (DSP)
- Configurable Nested Vectored Interrumpere Controller (NVIC)
- Una Subtilitas fluctuetur Unit (FPU)
• Pro interfaces
- 4 - 40 MHz oscillator externum festinanter (SOSC) cum usque ad 50 MHz DC externum quadratum input horologii in modo horologii externi.
– 48 MHz Fast Internum RC oscillator (FIRC)
– 8 MHz Tardus Internus RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
- Ad CXII MHz (HSRUN) Ratio sursum Phased Loop (SPLL)
– Ad 20 MHz TCLK et 25 MHz SWD_CLK
– 32 kHz Real Time Contra horologium externum (RTC_CLKIN)
• Potestas procuratio
- Low-power bracchium Cortex-M4F/M0+ core cum excellenti industria efficientiae
- Potestas Management Controller (PMC) multis modis potentiae: HSRUN, CURSUS, STOP, VLPR, VLPS.Nota: CSEc (Securitas) vel EEPROM scribens/ dele erit trigger errorum vexilla in mode HSRUN (112 MHz) quia hic usus casus simul exsequi non licet.Cogitatus necesse erit ut modum currendi currendi (80 MHz) ad exsequendum CSEc (Securitatis) vel EEPROM scribens / dele.
– Horologium perceptio et humilis operatio virtutis certis periphericis sustinetur.
• memoria et memoria interfaces
- Ad II MB progressio mico memoria cum ECC
– 64 KB FlexNVM memoriae pro notitia emicare cum ECC et EEPROM aemulatione.Nota: CSEc (Securitas) vel EEPROM scribens/radere erit felis errorum vexilla in mode HSRUN (112 MHz) quia hic usus casus simul exsequi non licet.Cogitatus necesse erit ut modum currendi currendi (80 MHz) ad exsequendum CSEc (Securitatis) vel EEPROM scribens / dele.
- Ad CCLVI KB SRAM cum ECC
- Ad IV KB of FlexRAM ad usum ut SRAM vel EEPROM aemulatio
- Ad 4 KB code cache ad latenciis accessum memoriae obscuratis perficiendi impulsum
- QuadSPI cum HyperBus™ firmamentum
• Signum Analog-mixtum
- Usque ad duos XII frenum Analog-ad-Digital Converter (ADC) cum usque ad XXXII channel Analog inputs per moduli
- One Analog Comparator (CMP) cum internis 8-bit Digital ad Analogia Converter (DAC)
• Debug functionality
- Serial Wire JTAG Debug Portus (SWJ-DP) combines
- Notice Watchpoint et Trace (DWT)
- Instrumentation Trace Macrocell (ITM)
- Expertus Portus Interface Unit (TPIU)
- Flash Patch et Breakpoint (FPB) Unit
• machina humana interface (HMI)
- Ad CLVI GPIO paxillos adjicias functionality
- Non Maskable adjicias (NMI)

• Communications interfaces
- Usque ad tres potentiae Low universalis Asynchronous Receptor/Transmitter (LPUART/LIN) modulorum cum DMA auxilio et potentia humilis disponibilitate
- Ad tria Low Power Serial interface periphericis (LPSPI) modulorum cum DMA auxilio et potentia humilis disponibilitate
- Usque ad duos Maximum Power inter Integrated Circuit (LPI2C) modulorum cum DMA auxilio et potentia humilis disponibilitate
- FlexCAN modulorum usque ad tres (cum libitum subsidium CAN-FD)
– FlexIO moduli ad aemulationem communicationis protocolla et peripheralium (UART, I2C, SPI, I2S, LIN, PWM, etc.).
- Usque ad unum X/100Mbps Ethernet cum IEEE1588 auxilio et duo Audio Synchroni interface (SAI) modulorum.
• Salutis et Securitatis
– Engineering Cryptographicae Services (CSEc) instrumentorum comprehensivorum functionum cryptographicarum quae in illa descriptae sunt (Secure Hardware Extension) Functional Specification.Nota: CSEc (Securitas) vel EEPROM scribens/radere erit felis errorum vexilla in mode HSRUN (112 MHz) quia hic usus casus simul exsequi non licet.Cogitatus necesse erit ut modum currendi currendi (80 MHz) ad exsequendum CSEc (Securitatis) vel EEPROM scribens / dele.
- 128-bit Unicum Lepidium sativum (ID) numerus
- Error-correcting Code (ECC) in mico et SRAM memorias
- Ratio Memoria Praesidium Unit (System MPU)
- Cyclic Redundancy Moderare (CRC) modulus
- Internus vigil (WDOG)
- Watchdog externus monitor (EWM) modulus
• Leo et imperium
- Usque ad octo independens XVI frenum FlexTimers (FTM) modulorum, offerens usque ad 64 canales vexillum (IC/OC/PWM)
- One 16-bit Low Power Timer (LPMR) flexibilibus excitare imperium
- Duo Programmable Mora obstruit (PDB) flexibili felis systema
- Una XXXII frenum Minimum Power interpella Timer (LPIT) in IV channels
- 32-bit Real Time Counter (RTC)
• Package
— 32 clavum QFN, 48 clavum LQFP, 64 clavum LQFP, 100 clavum LQFP, 100 clavum MAPBGA, 144 clavum LQFP, 176 clavum LQFP involucrum bene
• 16 alveum DMA cum fontibus petentibus usque ad 63 utens DMAMUX