LCMXO2-2000HC-4BG256C FPGA - Gate Programmabili Array 2112 LUTs 207 IO 3.3V 4 Spd
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | cancellos |
| Product Category: | FPGA - Field Programmabiles portae Array |
| RoHS: | Singula |
| Series: | LCMXO2 |
| Numerus Elementorum Logicae: | 2112 LE |
| Numerus I / Os: | 206 I/O |
| Supple intentione - Min: | 2.375 V |
| Supple intentione - Max: | 3.6 V |
| Minimum Operating Temperature: | 0 C |
| Maximum Operating Temperature: | + 85 C |
| Data Rate: | - |
| Numerus Transceivers: | - |
| Adscendens Style: | SMD/SMT |
| Sarcina / Case: | CABGA-256 |
| Packaging: | Tray |
| Notam: | cancellos |
| RAM distribuit: | 16 kbit |
| Embedded Clausus RAM - EBR: | 74 kbit |
| Maximum Operating Frequency: | 269 MHz |
| Humor Sensitivus: | Ita |
| Numerus Logicae Forum obstruit - LABs: | 264 LAB |
| Supple Current operating: | 4.8 mA |
| Supple intentione operating: | 2.5 V/3.3 V |
| Product Type: | FPGA - Field Programmabiles portae Array |
| Factory Pack Quantity: | 119 |
| Subcategoria: | Programmabilis Logica ICs |
| Summa Memoria: | 170 kbit |
| Nomen: | MachXO2 |
| Unitas pondus: | 0.429319 oz |
1. Flexibile Architectura Logica
• Sex machinis cum 256 ad 6864 LUT4s et 18 ad 334 I/Os Ultra Low Power Devices
• LXV nm Advanced potentia processus humilis
• sicut humilis ac 22 μW standby potentia
• Programmable adductius humilis differentialis I / Os
• Sta-per modum et alias potestates optiones salutaris 2. Memoria embedded et Distributa
• Ad CCXL kbits sysMEM™ Embedded Clausus RAM
• Ad LIV kbits Distributed RAM
• Dedicated FIFO control logicae
3. De-Chip User Flash Memoria
• Sursum ad CCLVI kbits User Flash Memoria
• 100,000 scribe cycles
• pervibiles per WISHBONE, SPI, I2 C et JTAG interfaces
• adhiberi potest ut mollis processus PROM aut sicut Flash memoria
4. Pre-ipsum Synchronum I / O *
• DDR registra in I/O cellulis
• dedicavit gearing logica
• VII: Apparatus ad Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicavit DDR / DDR2 / LPDDR memoria cum DQS firmamentum
5. Maximum euismod, flexibile I/O Buffer
• Programmabile syIO™ quiddam sustinet amplis interfacium:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
- LVTTL
- PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL .
– SSTL 25/18
– HSTL 18
- Schmitt felis initibus, usque ad 0.5 V hysteresis
• I / os calidum socketing support
• De-chip terminationem differentialem
• Programmable viverra-sursum vel viverra-descendit modus
6. Flexibile De Chip clocking
• octo prima horologiorum
• Ad duo ora horologiorum summus celeritas I / O interfaces (imo utrimque modo)
• Ad duo Analog PLLs per fabrica cum fracti-n frequentia synthesis
- Lata initus frequency range (VII MHz ad CD MHz)
7. Non volatile, Infinite Reconfigurable
• instantes-on
- potentiae in microseconds
• Single-chip, securam solutionem
• Programmabile per JTAG, SPI vel I2 C
• background programmatio subsidia de non-vola
8.tile memoria
• Dual tabernus cum externum SPI memoria libitum
9. TransFR™ Reconfigurationis
• in-agro ratione update dum ratio operatur
10. Consectetur Ratio Level Support
• Munera obdurata de chip: SPI, I2 C, timer/
• De-chip oscillator cum 5.5% accurate
• Unique TraceID ad systema tracking
• unus tempus Programmable (OTP) modus
• Una potentia copia operating range extenso
• IEEE Standard 1149,1.
• IEEE 1532 ratio programmatis obsecundans
11. plateae latioris range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN involucrum bene
• Parvus vestigium sarcina optiones
- Ut minima quam 2.5 mm x 2.5 mm
• densitas transitus confirmavit
• Provectus halogen-liberum packaging
