SN65DSI84TPAPRQ1 Auto Sngl Ch MIPI DSI ad SnglLink LVDS
Product Description
Productum attributum | Precium attributum |
Fabrica: | Texas Instrumenta |
Product Category: | LVDS Interface IC |
Typus: | DSI ad Dual-Link LVDS Bridge |
Numerus Coegi: | VIII Coegi |
Numerus receptorum: | 4 receptor |
Data Rate: | 1.078 Gb/s |
Input Type: | MIPI D-PHY |
Output Type: | LVDS |
Supple intentione - Max: | 1.95 V |
Supple intentione - Min: | 1.65 V |
Minimum Operating Temperature: | - 40 C |
Maximum Operating Temperature: | + 105 C |
Adscendens Style: | SMD/SMT |
Sarcina / Case: | HTQFP-64 |
Quid: | AEC-Q100 |
Packaging: | Reel |
Packaging: | Cut Tape |
Packaging: | MouseReel |
Notam: | Texas Instrumenta |
Humor Sensitivus: | Ita |
Supple Current operating: | 106 mA |
Product Type: | LVDS Interface IC |
Series: | SN65DSI84-Q1 |
Factory Pack Quantity: | 1000 |
Subcategoria: | Interface ICs |
Unitas pondus: | 0.010780 oz |
SN65DSI84-Q1 Automotive Single Channel MIPI® DSI ad Dual-Link LVDS Bridge
SN65DSI84-Q1 DSI-ad-LVDS pontis notat unum alveum MIPI D-PHY receptaculum ante-finis conformationis cum quattuor vicis per canalem operantem in 1 Gbps per lane et maximam input latitudinem 4 Gbps.Pons MIPI® DSI 18-bpp RGB666 et 24-bpp RGB888 decedit et in LVDS output operantem in pixel horologiorum data-fluminis ad LVDS operantem operantem a 25 MHz ad 154 MHz, offerens nexum LVDS vel unicum nexum LVDS cum quattuor vicis data per nexum.
SN65DSI84-Q1 fabrica bene apta est WUXGA (1920 1080) ad 60 tabulas per secundam (fps) cum usque ad 24 particulas per-pixel (bpp).Linea partialis buffering ad effectum deduci potest ad accommodare mismatch notitias fluminis inter interfacies DSI et LVDS.
Fabrica SN65DSI84-Q1 in parva adumbratione perficitur 10 mm × 10 mm HTQFP involucrum cum pice 0,5-mm, et trans range temperatura ab -40°C ad 105°C operatur.
I • idoneus pro Automotive Applications
• AEC-Q100 secundum quid cum Proventus:
- Fabrica Temperature Gradus 2: -40°C ad CV°C Ambiens Operating Temperature
- Fabrica HBM ESD Ordo Level 3A
- Fabrica CDM ESD Classification Level C6
• Implementa MIPI D-PHY Version 1.00.00 Corporalis Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
• Single Channel DSI receptor configurable pro uno, duobus, tribus, vel quatuor D-PHY Data Lancs Per Channel Operans usque ad I Gbps Per Lane
• subsidia XVIII-bpp et XXIV-bpp DSI Video Packets cum RGB666 et RGB888 Formats
• Apta pro 60-fps WUXGA 1920 × 1200 Resolutio in 18-bpp et 24-bpp Colore, ac 60- fps 1366 × 768 Resolutio in 18-bpp et 24-bpp.
• Output configurable for Single-Link or Dual-Link LVDS
• subsidia Single canali DSI ad Dual-Link LVDS Modus Operating
• LVDS Output-Clock dolor 25 MHz ad 154 MHz in Dual-Link or Single-Link Modus
• LVDS Pixel Horologium potest esse ex FreeRunning Continua D-PHY Horologium seu externi Reference Horologium (REFCLK)
• 1.8 V Praecipua VCC Power Supple
• Low Power Features Include Modus shutdown, Reducitur LVDS output intentione adductius, Modus communis, et MIPI Ultra-Maximum Potestas Civitatis (ULPS) Support
• LVDS Channel RES, LVDS ACUS Ordinis inversa Feature ad sublevandam PCB Routing
• Packaged in 64-pin 10 mm 10 mm HTQFP (PAP) PowerPAD™ IC Package
• Infotainment Caput Unit Cum Integrated Display
• Infotainment Caput Unit Cum Longinquus Display
• Infotainment Tergo-Sedes Entertainment
• Hybrid Automotive Botri
• Portable Navigation Fabrica (PND)
• Navigatio
• Industrial Humanum Machina interface (HMI) et Displays