SPC563M64L5COAR 32-bit Microcontrollers – MCU 32-BITUM Embedded MCU 80 MHz, 1.5 Mbyte
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | STMicroelectronics |
| Product Category: | 32-bit Microcontrollers - MCU |
| RoHS: | Singula |
| Series: | SPC563M64L5 |
| Adscendens Style: | SMD/SMT |
| Sarcina / Causa: | LQFP-144 |
| Core: | e200z335 |
| Programma Memoria Location: | 1.5 MB |
| Data Ram Size: | 94 kB |
| Data Bus Latitudo: | 32 bit |
| ADC Consilium: | 2 x 8 bit/10 bit/12 bit |
| Maximum Horologium Frequency: | 80 MHz |
| Numerus I / Os: | 105 I/O |
| Supple intentione - Min: | 5 V |
| Supple intentione - Max: | 5 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 125 C |
| Quid: | AEC-Q100 |
| Packaging: | Reel |
| Packaging: | Cut Tape |
| Packaging: | MouseReel |
| Notam: | STMicroelectronics |
| Humor Sensitivus: | Ita |
| Product Type: | 32-bit Microcontrollers - MCU |
| Factory Pack Quantity: | 500 |
| Subcategoria: | Microcontrollers - MCU |
| Unitas pondus: | 1.290 g |
♠ 32-bit Power Architecture® based MCU for automotive powertrain applications
Hae 32-bitrae autocinetorum microcontrollorum sunt familiae systematis-on-Chip (SoC) machinis quae multa novas notas cum summa observantia continentes 90 nm CMOS technologiam substantialem reductionem sumptus per plumam ac praestantiam praestantiam praestant.Provectus et sumptus efficens nucleus processus exercitus huius autocineti moderatoris familiae in technologia Power Architecture® aedificatur.Haec familia amplificationes continet quae aptas architecturae in applicationibus immersis emendant, additicium instructionis subsidium pro Processing Digital (DSP), technologias integrant - sicut unitas temporis auctus processus, auctus analogicus ad digital converter, Controller Area Network et auctus modularis input-output ratio - quae momenti sunt pro hodiernis applicationibus ad extremum powertrain.Cogitatus unicum gradum hierarchiae memoriae habet, constans usque ad 94 KB in chip SRAM et usque ad 1.5 MB memoriae mico internae.Etiam machinam Bus Interface (EBI) pro 'calibratione' habet.
■ Unius exitus, 32 frenum Power Architecture® Liber E obsequentem e200z335 CPU nucleum complexum.
- Includes Variabilis Longitudo Encoding (VLE) enhancements ad codicem magnitudine reductionem
■ 32-canale Direct Memoria Access moderatoris (DMA)
■ Interrumpere Controller (INTC) tractandi capax 364 fontes selectable-prioritatis interruptio: 191 fontes peripherales interrumpunt, 8 programmata obloquitur et 165 interrumpit reservata.
■ Frequency-Modulated Phase-Loop Locked (FMPLL)
■ Calibration Bus Interface (EBI)(a)
■ System Integration Unit (SIU)
■ Sursum ad 1.5 Mbyte in-chip Flash cum Flash controller
- Da Accelerator pro uno cyclo Flash accessum @ LXXX MHz
■ Sursum ad XCIV Kbyte on-chip static RAM (including usque ad XXXII Kbyte sto RAM)
■ Tabernus adiuva amet (BAM)
■ 32- alveus secundae generationis auctus Tempus Processoris Unit (eTPU)
- 32 vexillum eTPU canales
- Architectural enhancements ad meliorem codicem efficientiam et flexibilitatem additae
■ 16-canales auctus Modularis Input-Output System (eMIOS)
■ Consectetur Queued Analog-ad-Digital Converter (eQADC)
■ Decimation filter (part of eQADC)
■ Pii mori temperatus sensorem
■ 2 Deserial Serial interface periphericis (DSPI) modulorum (compatible cum Microsecond Bus)
■ 2 aucta Serial Communicatio interface (eSCI) modulorum compatibilis cum LIN
■ 2 Controller Area Network (FlexCAN) modulorum sustentantium CAN 2.0B
■ Nexus Port Controller (NPC) per IEEE-ISTO 5001-2003 standard
■ IEEE 1149.1 (JTAG) firmamentum
■ Nexus interface
■ De-chip intentionis moderatoris moderatoris, qui 1.2 V et 3.3 V commeatum internum ab a 5 V principio externo praebet.
■ Designed for LQFP144, and LQFP176
