STM32F105VCT6 ARM Microcontrollerers – MCU 32BIT Cortex 64/25 CONNECTIVITAS LINE M3
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | STMicroelectronics |
| Product Category: | ARM Microcontrollers - MCU |
| Series: | STM32F105VC |
| Adscendens Style: | SMD/SMT |
| Sarcina / Case: | LQFP-100 |
| Core: | ARM Cortex M3 |
| Programma Memoria Location: | 256 kB |
| Data Bus Latitudo: | 32 bit |
| ADC Consilium: | 12 bit |
| Maximum Horologium Frequency: | 72 MHz |
| Numerus I / Os: | 80 I/O |
| Data Ram Size: | 64 kB |
| Supple intentione - Min: | 2 V |
| Supple intentione - Max: | 3.6 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 85 C |
| Packaging: | Tray |
| Notam: | STMicroelectronics |
| Data RAM Type: | SRAM |
| Height: | 1.4 mm |
| Interface Type: | CAN, I2C, SPI, USART . |
| Longitudo; | 14 mm |
| Humor Sensitivus: | Ita |
| Numerus ADC canales: | 16 Channel |
| Numerus Timers / Calculis: | 10 Timer |
| Processus Series: | ARM Cortex M |
| Product Type: | ARM Microcontrollers - MCU |
| Programma Memoria Type: | Flash |
| Factory Pack Quantity: | 540 |
| Subcategoria: | Microcontrollers - MCU |
| Nomen: | STM32 |
| Latitudo: | 14 mm |
| Unitas pondus: | 0.041530 oz |
• Core: ARM® 32-bit Cortex®-M3 CPU – 72 MHz frequentia maxima, 1.25 DMIPS/MHz (Dhrystone 2.1) effectus in 0 exspectatione status memoria accessus
- Singulus cyclus multiplicatio et hardware divisio
• Memoriae
- 64 ad 256 Kbytes de Mico memoria
- 64 Kbytes generalis consilii SRAM
• Horologium, reset ac copia administratione
- 2.0 ad 3.6 V applicationis copia et I/Os
- POR, PDR et programmabilis intentione detectoris (PVD)
- 3-ad-25 MHz crystallum oscillatorium
- Internum 8 MHz officinas-ornata RC
- Internum 40 kHz RC cum calibration
- 32 kHz oscillator pro RTC cum calibratione
• Maximum imperium
- Somnus, Siste et sto modos
- VBAT supple pro RTC et tergum registris
• 2 × 12-bit, 1 µs A/D convertentium (16 canales)
- Conversio range: 0 ad 3.6 V
- Sample ac tenere facultatem
- Temperature sensorem
- usque ad II MSPS in interleaved modus
• 2 12-bit D/A converters
• DMA: 12-fluvium DMA controller
- Subnixi peripherales: timers, ADCs, DAC, I2Ss, SPIs, I2Cs et USARTs
• Debug modus
- Serial filum debug (SWD) & JTAG interfaces
- Cortex®-M3 Embedded Trace Macrocell™
• Ad LXXX ieiunium I / O portus
– 51/80 I/Os, omnia mappabilia in 16 vectoribus externis interrumpentibus et fere omnibus 5 V tolerantibus
• CRC unitas calculi, 96-bit singularis ID
• Sursum ad X timers cum pinout remap facultatem
- Usque ad quattuor 16-bit timers, unaquaeque cum usque ad 4 IC/OC/PWM vel pulsus calculo et quadratura (incrementalis) encoder initus
- 1 16-bit motricium imperium PWM timer cum mortuis generationibus et subitis stop
- 2 watchdog timers (Iuris et Fenestra)
- SysTick timer: a XXIV-bit downcounter
- 2 16-aliquantulus basic timers ut expellam DAC
• Ad XIV communicatio interfaces pinout remap facultatem
- Ad 2 I2C interfaces (SMBus/PMBus)
- Usque ad 5 USARTs (ISO 7816 interface, LIN, IrDA facultatem, modem imperium)
- Sursum ad 3 SPIs (18 Mbit/s), 2 cum multiplicata I2S interface quae praebet audio genus accurationem per progressionem PLL machinas
– 2 interfacet (2.0B Active) cum 512 bytes dedicavit SRAM
- USB 2.0 plena celeritate fabrica / exercitum / OTG controller cum on-chip PHY sustentans HNP/SRP/ID cum 1.25 Kbytes de dedicated SRAM
– 10/100 Aer MAC cum dicatis DMA et SRAM (4 Kbytes): IEEE1588 subsidia ferramenta, MII/RMII in omnibus fasciculis praesto
