TMS320VC5509AZAY Processus Digitalis Signalis & Moderatores - DSP, DSC Fixum-Point Processus Digitalis 179-NFBGA -40 ad 85
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | Texas Instrumenta |
| Product Category: | Digital Signum Processores & Moderatores - DSP, DSC |
| RoHS: | Singula |
| Productum: | DSPs |
| Series: | TMS320VC5509A |
| Adscendens Style: | SMD/SMT |
| Sarcina / Causa: | NFBGA-179 |
| Core: | C55x |
| Numerus Cores: | 1 Core |
| Maximum Horologium Frequency: | 200 MHz |
| L1 Cache Instructio Memoria: | - |
| L1 Cache Data Memoria: | - |
| Programma Memoria Location: | 64 kB |
| Data Ram Size: | 256 kB |
| Supple intentione operating: | 1.6 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 85 C |
| Packaging: | Tray |
| Notam: | Texas Instrumenta |
| Instructio Type: | Certum punctum |
| Interface Type: | I2C |
| Humor Sensitivus: | Ita |
| Product Type: | DSP - Digital signum Processors & Controllers |
| Factory Pack Quantity: | 160 |
| Subcategoria: | Embedded Processors & Controllers |
| Supple intentione - Max: | 1.65 V |
| Supple intentione - Min: | 1.55 V |
| Watchdog Timers: | Watchdog Timer |
TMS320VC5509A Fixarum-Point Digital Signum Processor
TMS320VC5509A fixum-punctum processus signum digitale (DSP) fundatur in generatione TMS320C55x DSP CPU processus nuclei.Architectura C55x™ DSP altam observantiam et humilem potestatem consequitur per parallelismum auctum et totum focus de reductione in potentia dissipationis.CPU bus structuram internam sustinet quae ex uno bus programmatis componitur, tres notitias negotiorum legunt, duae notitiae negotiationes scribentes, et additamenta negotialis periphericis et DMA actui dicata.Hi buses facultatem praebent perficiendi usque ad tres notitias legentium et duas notitias scribens in uno cyclo.Parallela DMA moderatoris ad duas translationes per cyclum sine actione CPU datas praestare potest.
C55x CPU duas unitates multiplicantes (MAC) multiplicantes praebet, quaelibet 17 bis x 17 bis multiplicatio in uno cyclo capax est.Pars media 40-bit arithmetica/logica unitas (ALU) suffragatur addito 16 frenum ALU.Usus ALUs sub disciplina potestate constitutus est, facultatem praebens ad consummationem parallelam actionis ac potentiae optimize.Hae facultates tractantur in Oratione Unit (AU) et Data Unit (DU) C55x CPU.
Generatio C55x DSP variabilem byte latitudinis institutionem sustinet pro meliore codice densitatis positae.Instructio Unitas (IU) facit 32-parum programmata ab interna vel externa memoria et queues instructiones ad Unitas Programma (PU).Unitas Programma instructiones decidit, munera ad UA et DU opes dirigit, ac fistulam plene munitam administrat.Facultas ramosa praeditiva vitat pipelineum rubet in executione instructionum conditionalium.
Communis propositi initus et output functiones ac the10-bit A/D sufficientes fibulas pro statu, interpellatione, et frenum I/O pro LCDs, claviaturis et instrumentis interfaces.Medium parallelum duobus modis operatur, vel ut servo microcontrolli utens portum HPI vel quasi instrumentorum parallelorum instrumentorum asynchrono EMIF utente.Serial instrumentis innixa per duos MultiMedia Card/Secre Digital (MMC/SD) periphericis et tribus McBSPs.
5509A paroecia peripherica includit memoriam externam interfaciem (EMIF) quae praebet accessum glutinosum ad memoriam asynchronam sicut EPROM et SRAM, necnon ad memoriam altae velocitatis, altae densitatis sicut synchrone DRAM.Additional peripherales includunt Universales Serial Bus (USB), horologium reale, timor vigil, I2C multi dominus et servi interface.Tres multi canali pleni-duplici opponunt portus Vide (McBSPs) glutinosam inter faciem praebent variis machinis serialis industriae, et communicationis multi canalis cum usque ad 128 canales separatim paraverunt.Auctus interfaciei exercitus (HPI) est 16 frenum parallelum instrumenti ad accessum ad accessum hospitem 32K bytes memoriae internae in 5509A.HPI configurari potest vel multiplex vel non multiplex modus, ut interfaciem glutinosam praebeat multitudini processuum multiformi.DMA moderatoris datas motus praebet sex contextum sine CPU interventum canalem independentem, praebens DMA per condicionem usque ad duo verba 16 bis per cyclum.Duo cursores generales propositi, usque ad octo clavos generales dedicatos I/O (GPIO) et fasciculum digitale-clausum (DPLL) generationis horologii comprehenduntur.
5509A industria conciliationis eXpressDSP™, Code Composer Studiorum Integrated Development Environment (IDE), DSP/BIOS™, Texas Instrumentorum algorithmus vexillum, et industriae maximae tertiae factionis ornatum.Code Composer Studio IDE notat codicem generationis instrumenta inclusis a C Compiler et Visual Linker, simulator, RTDX™, XDS510 ™ aemulatio fabrica coegi, et modulorum aestimatio.5509A etiam Bibliotheca C55x DSP adiuvatur, quae plus quam 50 nuclei nuclei fundamenti (FIR filtra, IIR filtra, FFTs, variae matheseos functiones) necnon chip et tabulas bibliothecas sustinent.
TMS320C55x DSP nucleus cum aperta architectura creatus est qui permittit additionem hardware specialium applicationis ad perficiendum in algorithmis specificis.Ferramenta extensiones in 5509A libram perfectam fixae functionis perficiendi cum programmabili flexibilitate percutiunt, cum consummationem vim humilem assequantur, et constant quod traditum difficile est invenire in foro video-processus.Extensiones permittunt 5509A liberare eximiam video codicam observantiam cum plusquam dimidia parte sua parata ad ulteriores functiones peragendas ut color spatii conversionis, operationum interfaciei, securitatis, TCP/IP, vocis agnitionis, et scripti ad conversionem sermonis.Quam ob rem, una 5509A DSP potissimas applicationes digitales videndi portatiles in potentiis potest cum processui headoris ad parcendum.Pro maiori, vide TMS320C55x Extensiones Hardware pro Image/Video Applications Programmationis referentiae (numerus litterarum SPRU098).Pro magis notitia de usura the DSP Image Processing Library, vide TMS320C55x Image/Video Processing Library Programmer's Reference (numerus litterarum SPRU037).
• Summus euismod, Low-Power, Fixum-Point TMS320C55x ™ Digital processor signum
9.26-, 6.95-, 5-ns Instructio Cycle Time
108-, 144-, 200-MHz Clock Rate
Unum/Duo Instructio (s) Actum per Cycle
Dual Multipliers [Ad CD Million Multiplicate-accumulat per Second (MMACS)]
Arithmetica Duo / Unitas Logica (ALUs)
Tres Internum Data / Operand Read Buses ac Duo Internum Data / Operand Write Buses
• 128K x 16-bit On-Chip RAM, Ex composito:
− 64K Bytes of Dual-Access Ram (DARAM) 8 Stipitibus 4K 16-Bit
− 192K Bytes of Single-Access RAM (SARAM) 24 Block of 4K 16-Bit
• 64K Bytes of One-Mane-Status De Chip ROM (32K × 16-Bit)
• 8M × 16-Bit Maximum Addressable Memoriae Externae Spatii (Synchronous DRAM)
• 16-bit Externi Parallel Bus Memoria sustentans Aut:
− Memoria externa instrumenti (EMIF) Cum Facultatibus GPIO et instrumenti glutinis ad:
Asynchronous Static RAM (SRAM)
Asynchronous EPROM
Synchroni DRAM (SDRAM)
16-bit Parallel Consectetur Host-Portus Interface (EHPI) Cum GPIO Capabilities
• Programmable Low-Power Control Sex Fabrica Eget Dominia
• De Chip Scan-Substructio aemulatio Logica
• De-Chip Peripherals
Duo XX-bit Timers
Watchdog Timer
Six Channel Direct Memoria Access (DMA) Controller
Tres Serial Portus deducto Supportantes:
Sursum in III Multichannel Buffered Serial portuum (McBSPs)
Ad II MultiMedia / Secure Digital Card interfaces
Programmable Phase-Loop Locked Horologium Generator
Septem (LQFP) vel Octo (BGA) Generalis-Propositum I/O (GPIO) paxillos et propositum generale Output Pin (XF)
− USB plena velocitate (12 Mbps) Servus Portus Molem Supportantes, interpella et translationes Isochronae
− Circuit inter Integrated (I2C) Multi-Magistri et Slavi interface
− Real-Tempus Pro (RTC) Cum Crystal Input, Separate Pro Domain, Separate Power Supple
4-canale (BGA) seu 2-canale (LQFP) 10-bit successiva approximatio A/D
• IEEE Std 1149.1† (JTAG) Terminus Scan Logicae
• Packages:
− 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH Suffix)
− 179-Terminal Lead-Free MicroStar BGA™ (Ball Grid Array) (ZHH Suffix)
• 1.2-V Core (108 MHz), 2.7-V - 3.6-VI/Os
• 1.35-V Core (144 MHz), 2.7-V - 3.6-VI/Os
• 1.6-V Core (200 MHz), 2.7-V - 3.6-VI/Os
• Hybrid, systema traminis electrica et potentia (EV/HEV)
- Pugna ratio administrationis (BMS)
- Ad tabulam patina
- Tractio inverter
- DC/DC converter
- Coepi / generans
