AM3352BZCZA100 Microprocessors - MPU ARM Cortex-A8 MPU
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | Texas Instrumenta |
| Product Category: | Microprocessors - MPU |
| RoHS: | Singula |
| Adscendens Style: | SMD/SMT |
| Sarcina / Causa: | PBGA-324 |
| Series: | AM3352 |
| Core: | ARM Cortex A8 |
| Numerus Cores: | 1 Core |
| Data Bus Latitudo: | 32 bit |
| Maximum Horologium Frequency: | 1 GHz |
| L1 Cache Instructio Memoria: | 32 kB |
| L1 Cache Data Memoria: | 32 kB |
| Supple intentione operating: | 1.325 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 125 C |
| Packaging: | Tray |
| Notam: | Texas Instrumenta |
| Data Ram Size: | 64 kB |
| Data ROM Size: | 176 kB |
| Progressus Ornamentum: | TMDXEVM3358 |
| I/O intentione: | 1.8 V, 3.3 V |
| Interface Type: | CAN, Aer, I2C, SPI, UART, USB . |
| L2 Cache Instructio / Data Memoria: | 256 kB |
| Memoria Type: | L1/L2/L3 Cache, RAM, ROM |
| Humor Sensitivus: | Ita |
| Numerus Timers / Calculis: | 8 Timer |
| Processus Series: | Sitara |
| Product Type: | Microprocessors - MPU |
| Factory Pack Quantity: | 126 |
| Subcategoria: | Microprocessors - MPU |
| Nomen: | Sitara |
| Watchdog Timers: | Watchdog Timer |
| Unitas pondus: | 1.714 g |
AM335x Sitara™ Processors
AM335x microprocessores, in processu ARM Cortex-A8 innixi, cum imagini, graphicis processui, periphericis, periphericis et industrialis optionum instrumentorum communicationis aucti sunt sicut EtherCAT et PROFIBUS.Cogitationes summus gradus systemata operandi sustinent (HLOS).Processus SDK Linux® et TI-RTOS praesto sunt sine pretio a TI.
In AM335x microprocessoris subsystematum continet subsystematum in Functional Clausi Diagramma demonstratum et brevem cuiusque sequitur descriptionem:
Subsystematum continet in Functionali Block Diagram exhibitum et brevem cuiusque sequitur descriptionem:
Microprocessor unitas (MPU) subsystem in processus ARM Cortex-A8 fundatur et PowerVR SGX™ Graphics Accelerator subsystem praebet accelerationem graphics 3D ad effectus sustinendos et effectus aleatorum.PRU-ICSS ab ARM core separatum est, operationem independentem praebens et clocking ad maiorem efficaciam et flexibilitatem.
PRU-ICSS dat accessiones interfaces peripherales et protocolla realia temporis ut EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Aer Powerlink, Sercos, et alii.Accedit ratio programmabilis naturae PRU-ICSS, cum accessu ad paxillos, eventus et omnes facultates systematis (SoC) , flexibilitatem praebet in exsequendo velocitate, responsionibus realibus temporis, specialibus notitiis pertractandis operationibus, consuetudine periphericis. atque in sudoribus aliis processoris SoC.
• Usque ad 1-GHz Sitara™ ARM® Cortex® -A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
– 32KB de L1 Instructione et 32KB datae Cache cum uno errore Deprehensio (paritas)
- 256KB of L2 Cache Cum Error Correctionis Code (ECC)
– 176KB of On-Chip Boot ROM
- 64KB of Dedicavit RAM
- Emulation et Debug - JTAG
- Interpellare Controller (usque ad CXXVIII interrumpere supplicum libellis)
• De-Chip Memoria (Shared L3 RAM)
- 64KB of General-Propositum On-Chip Memoria Controller (OCMC) RAM
- Ad omnes Masters promptu
- Sustinet retentione pro Fast Wakeup
• Memoria externa interfaces (EMIF)
– mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
- mDDR: 200-MHz Horologium (CD-MHz Data Rate)
- DDR2: 266-MHz Horologium (532-MHz Data Rate)
- DDR3: 400-MHz Horologium (DCCC-MHz Data Rate)
- DDR3L: 400-MHz Horologium (DCCC-MHz Data Rate)
- 16-bit Data Bus
- 1GB totius Addressable Space
- subsidia una x16 vel duae x8 Memoria Fabrica configurationis
- General-Propositum Memoria Controller (GPMC)
- Flexibile 8-bit et 16-bit Asynchronae Memoriae instrumenti usque ad Septem Drachmas Selecta (NAND, NOR, Muxed-NOR, SRAM)
- Usus BCH Code ut suscipe 4-, 8-, vel 16-bit ECC
- Usus Hamming Code ut suscipe I-bit ECC
- Error Locator OMNIBUS (ELM)
- Usus in Conjunctione Cum GPMC ad Locare Inscriptiones Data Errorum Syndrome Polynomiales Generatae Utendo BCH Algorithmo
- subsidia 4-, 8- et XVI-bit per DXII-Byte Clausus Error Location Ex BCH Algorithms
• Programmable Real-time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Protocolla subsidia ut EtherCAT®, PROFIBUS, PROFINET, AERNET/IP™, ac More
- Duo Programmable Real-time Unitates (PRUs)
- 32-bit Load/Store RISC Processor Capable of Running at 200 MHz
- 8kb Instructionis ram Cum Single-Error Deprehensio (par)
- 8KB of Data Ram Cum Single-Error Deprehensio (paritas)
- Single Cycle XXXII-bit Multiplier Cum LXIV-bit Accumulator
- Consectetur GPIO amet praebet Shift in / de Support et parallela Claustrum in externi signum
- 12KB of Ram Shared Cum Single-Error Deprehensio (paritas)
- Tres 120-Byte Register Banks promptu per singulos PRU
- Interpellare Controller (INTC) pro tractantem ratio potenti Events
- Loci Interconnect Bus pro Dominis internis et externis connectere ad Resources intra PRU-ICSS
- Peripherales Intus PRU-ICSS:
- unus UART Portus Cum flow Imperium acus subsidia ad XII Mbps
- One Consectetur Captura (eCAP) OMNIBUS
- Duo MII Aer portus qui Aer Industrial Support, ut EtherCAT
- One MDIO Port
• Potestas, Reset et Horologium Procuratio (PRCM) Module
- Controls ingressu et Exitu sta-By et profundus-Somnus Modi
- Responsible for Somnus Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Horologiorum
- Integrated 15. ad XXXV-MHz summus Frequency Oscillator Generare solebat Horologium Reference pro Variis Systematis Periphericis & Horologiis
- subsidia singula Horologium activare et inactivare Imperium pro Subsystems et Peripherals ad facilius reducta Power consummatio
– Quinque ADPLLs ad Systema Horologiorum Generandum (MPU Subsystem, DDR Interface, USB et Peripherales [MMC et SD, UART, SPI, I 2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Horologium)
- Power
- Duo Power Domain Nonswitchable (Verus Tempus Horologium [RTC], Surge Logica [WAKEUP])
– Tres potestates Switchable Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherales et infrastructure [PER])
– Implementa SmartReflex™ Classis 2B pro Core intentione Scaling Substructio Die Temperature, Processu Variationis, et euismod (Adaptive intentione Scaling [AVS])
- Dynamic intentione Frequency Scaling (DVFS)
• Verus-Tempus Pro (RTC)
- Verus-Tempus Date (diei-mense-anno-diei Hebdomadae) et tempus (Horae-Minutes-Secundae) Information
- Internus 32.768-kHz Oscillator, RTC Logicus et 1.1-V Internus LDO .
- Independent-in-Reset (RTC_PWRONRSTn) Input
- Dedicavit Input Pin (EXT_WAKEUP) pro Externi Wake Events
- Programmable Terror adhiberi potest ad generandum Internum interpellationibus ad PRCM (pro Wakeup) vel Cortex-A8 (pro Vicis Notification)
– Programmabilis Terror adhiberi potest cum Output externi (PMIC_POWER_EN) ut Potestatem Management IC ad Domains Non RTC Restituere
• Peripherals
- Ad Duo USB 2.0 summus Volo DRD (Dual Partes Fabrica) portuum Integrated PHY
– Ad Gigabit Ethernet MACs Duobus Industrialibus (10, 100, 1000 Mbps)
- Integrated Switch
- MAC singula subsidia MII, RMII, RGMII, et MDIO interfaces
- Aer MACs et SWITCH PB potest operari independenter ab aliis functionibus
- IEEE 1588v1 Precision Time Protocol (PTP)
- Ad Duo Controller-Area Network (can) Portuum
- Supports POTEST in Versione 2 Partibus A et B
- Ad Duo Multichannel Audio portuum (MCASPs)
- Transmit et Accipite Horologiis ad L MHz
- Ad quattuor Serial Data paxillos per McASP Portus Cum Lorem TX et RX Clocks
- Tempus Division Multiplexing (TDM), Inter-IC Sonum (I2S), et Similia Formata
- Supports Digital Audio Interface Transmissio (SPDIF, IEC60958-1, et AES-III Formats)
- FIFO Buffers pro Transmit et Accipite (256 Bytes)
- Ad Sex UARTs
- Omnes UARTs Support IrDA et CIR Modi
- Omnes UARTs Support RTS et CTS O Imperium
- UART1 subsidia plena modem Imperium
- Ad Duo Magister et Servus McSPI Serial interfaces
- Ad Duo Chip Eligit
- Ad XLVIII MHz
- Ad Tres MMC, SD, SDIO Portus
- 1-, 4- et 8-Bit MMC, SD, SDIO Modes
- MMCSD0 dedicavit Power Rail ad 1.8'V vel 3.3-V Operatio
- Ad XLVIII-MHz data serie Rate
- subsidia Card deprehendere et scribere Protect
– Prosequitur MMC4.3, SD, SDIO 2.0 Specifications
- Ad Tres I 2C Magister et Servus Interfaces
- Modus Latin (usque ad 100 kHz)
- Fast Modus (usque ad CD kHz)
- Ad quattuor ripas Generalis-Propositum I/O (GPIO) Pins
- XXXII GPIO acus per Bank (multiplexed cum Aliae acus)
- GPIO acus adhiberi potest pro interpellare Inputs (usque ad Duo Interrumpere Inputs per Bank)
- Usque ad Tres Externi DMA Event Inputs qui etiam adhiberi possunt ut Interpellare Inputs
- Octo XXXII Bit Generalis-Propositum Timers
- DMTIMER1 est 1-ms Timer Used pro Operating System (OS) Ticks
- DMTIMER4-DMTIMER7 sunt confixi
- Unus Watchdog Timer
- SGX530 3D Graphics Engine
- Tile-Substructio Architecture tradens usque ad XX Million Polygonorum per Second
- Universalis Scalable Shader Engine (USSE) est Multithreaded Engine Incorporandi Pixel et Vertex Shader Functionality
- Provectus Shader Pluma in Excessu Microsoft VS3.0, PS3.0, et OGL2.0
- Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 et 2.0, et OpenMax.
- Fine-Grained Negotium Switching, Load Librans, and Power Management
- Provectus Geometria DMA agitatae Operatio ad minimum CPU Interaction
- Programmable High Quality Image Anti-aliasing
- Virtualized Memoria Plene Oratio pro OS Operationis in una Memoria Architecture
• Pellentesque Peripherals
• Domus et Industrial Automation
• Consumer Medical Appliances
• Printers
• Smart toll Systems
• Connected Vending Machinis
• perpendens squamae
• General Consoles
• Provectus Toys
