SPC5634MF2MLQ80 32-bit Microcontrolers – MCU NXP 32 frenum MCU, Core Virtutis Arch, 1.5MB Flash, 80MHz, -40/+125degC, Gradus Automotivus, QFP 144
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | NXP |
| Product Category: | 32-bit Microcontrollers - MCU |
| RoHS: | Singula |
| Series: | MPC5634M |
| Adscendens Style: | SMD/SMT |
| Sarcina / Causa: | LQFP-144 |
| Core: | e200z3 |
| Programma Memoria Location: | 1.5 MB |
| Data Ram Size: | 94 kB |
| Data Bus Latitudo: | 32 bit |
| ADC Consilium: | 2 x 8 bit/10 bit/12 bit |
| Maximum Horologium Frequency: | 80 MHz |
| Numerus I / Os: | 80 I/O |
| Supple intentione - Min: | 1.14 V |
| Supple intentione - Max: | 1.32 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 150 C |
| Quid: | AEC-Q100 |
| Packaging: | Tray |
| Analogia Supple intentione: | 5.25 V |
| Notam: | NXP Semiconductors |
| Data RAM Type: | SRAM |
| I/O intentione: | 5.25 V |
| Humor Sensitivus: | Ita |
| Productum: | MCU |
| Product Type: | 32-bit Microcontrollers - MCU |
| Programma Memoria Type: | Flash |
| Factory Pack Quantity: | 60 |
| Subcategoria: | Microcontrollers - MCU |
| Watchdog Timers: | Watchdog Timer |
| Pars # Aliases: | 935311091557 |
| Unitas pondus: | 1.319 g |
32-bit Microcontrollers - MCU
Hae 32-frenum autocinetorum microcontrollorum sunt familiae systematis (SoC) machinis quae omnes lineamenta familiae MPC5500 continent et multa nova notae cum summa observantia 90 nm CMOS coniunctae sunt ad solidam reductionem sumptus per plumam et significantes. perficiendi emendationem.Provectus et sumptus efficens nucleus processus exercitus huius autocineti moderatoris familiae in technologia Power Architecture® aedificatur.Haec familia amplificationes continet quae aptas architecturae in applicationibus immersis emendant, additicium instructionis subsidium pro signo processus digitalis (DSP), technologias integrant - sicut unitas temporis auctus processus, auctus queued analog-ad digital converter, Controller Area Network, ac auctus modularis input-output ratio - quae momenti sunt pro hodiernis applicationibus ad extremum powertrain.Haec familia fabrica omnino compatibilis est extensio ad familiam Freescale MPC5500.Cogitatus unicum gradum hierarchiae memoriae habet, constans usque ad 94 KB in chip SRAM et usque ad 1.5 MB memoriae mico internae.Etiam fabrica bus interfaciei (EBI) externam pro 'calibratione' habet.Haec bus interfacius externus designatus est ad memoriam maxime sustinendam cum MPC5xx et MPC55xx familiis.
• Operating Morbi
— Operatio stataria plene, 0 MHz- 80 MHz (plus 2% frequentiae modulatio- 82 MHz)
- 40 ad 150 confluentes temperatus operating range
- Minimum potentia design
- Minus quam potentia dissipationis mW CD (nominal)
- Designed for dynamic power management of core and peripherals
- Software imperium horologium porta peripherals
- Low stop modus virtutis, cum omnibus horologiis constitit
- Fabricata in XC nm processum
— 1.2 V logica interna
- Unius potentiae copiae cum 5.0 V -10％/+5% (4.5 V ad 5.25 V) cum moderatore interno providendi 3.3 V et 1.2 V pro core
- Input and output paxilli cum 5.0 V -10％/+5% (4.5 V ad 5.25 V) range
- 35%/65% VDDE CMOS switch gradus (cum hysteresi)
- Selectable hysteresis
- Selectable imperium rate percussit
- Nexus paxillos 3.3 V copia
- Designed with Tactus reductiones techniques
- Phase-clausa loop
- Frequency modulatio systematis horologii frequency
- De chip bypass capacitance
- Selectable rate et coegi vires percussit
• High perficientur e200z335 core processor
- 32-bit Power Architecture Book E programmarii exemplar
- Variabilis Longitudo Encoding Enhancements
- Potestatem Architecturae disciplinam paro ut optione encoded in mixto 16 et 32-bit instructiones
- Results in minor codice magnitudine
- Unius exitus, 32 frenum Power Architecture technologiae facilis CPU
- In ordine supplicium et secessum
- exceptione ipsum pertractatio
- unitas germen processus
- Dedicavit genere electronica vipera calculum
- Buffer germen accelerationis usus Lookahead Instructio germen
- Lond / copia unitatis
- One-cyclus latency onus
- Plene pipelined
- Magnus et Parva Endian firmamentum
- Misaligned accessum firmamentum
- Nulla onus-ut-usus pipeline bullae
- Triginta duo 64-bit generalis propositi tabulae (GPRs)
- Memoria procuratio unitatis (MMU) cum 16-introitu translationis plene adsociantis quiddam intuentibus (TLB)
- Singula disciplinam bus et onus / copia bus
- Vectored auxilium adjicias
- Interrumpere latency < 120 ns @ 80 MHz (ex interpellatione ad executionem primae instructionis interpellandi exceptionem tracto metiri)
