SPC5644AF0MLU2 32-bit Microcontrollers - MCU 32BIT3MB Flsh192KRAM
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | NXP |
| Product Category: | 32-bit Microcontrollers - MCU |
| RoHS: | Singula |
| Series: | MPC5644A |
| Adscendens Style: | SMD/SMT |
| Core: | e200z4 |
| Programma Memoria Location: | 4 MB |
| Data Ram Size: | 192 kB |
| Data Bus Latitudo: | 32 bit |
| Maximum Horologium Frequency: | 120 MHz |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 125 C |
| Quid: | AEC-Q100 |
| Packaging: | Tray |
| Notam: | NXP Semiconductors |
| Humor Sensitivus: | Ita |
| Processus Series: | MPC5644A |
| Product Type: | 32-bit Microcontrollers - MCU |
| Factory Pack Quantity: | 200 |
| Subcategoria: | Microcontrollers - MCU |
| Pars # Aliases: | 935321662557 |
| Unitas pondus: | 1.868 g |
32-bit Microcontrollers - MCU
e200z4 nucleus exercitus microcontrollerus processus in potentia technologiae architecturae aedificatus est et nominatim ad applicationes infixas disposita.Praeter Virtutis Architecturae technologiam, hoc nucleus instructiones ad signum processus digitalis sustinet (DSP).MPC5644A duos gradus hierarchiae memoriae habet, quibus constat 8 KB cache instructionis, subnixum per 192 KB in chip SRAM et 4 MB memoriae mico internae.
MPC5644A bus externam interfaciem includit, et etiam bus calibrationis tantum accessibilis est cum Systemate calibrationis Freescale VertiCal.Hoc documentum lineas MPC5644A describit et elucidat notas electricas et physicas momenti machinationis.
• 150 MHz e200z4 Power Architecture core
- Variabilis longitudo disciplinam modum translitterandi (VLE)
- Architectura Superscalaris cum II unitates supplicium
- Ad II integer vel fluctuetur instructiones per cycle
- Usque ad 4 multiplica et cumulare res per cyclum
• Memoria ordo
- IV MB in-chip mico memoria cum ECC et lege dum Write (RWW)
— 192 KB on-chip SRAM with standby functionality (32 MB) and ECC
- VIII KB disciplinam cache (cum linea densis), configurable ut 2. vel IV-modo
— 14 + 3 KB eTPU codice ac data RAM .
— 5 4 perticam switch (XBAR)
- 24-ingressum MMU
- Bus Interface (EBI) cum servo ac domino portum
• Fail Tutus Praesidium
- 16-introitus Memoria Protectionis Unit (MPU)
- CRC unitas cum 3 sub-modules
- Junction temperatus sensorem
• obloquitur
- Configurable adjicias moderatoris (cum NMI)
— 64-fluvium DMA
• Vide canales
- 3 eSCI
— 3 DSPI (2 quarum support amni Micro Secundi Channel [MSC])
- 3 FlexCAN cum 64 nuntiis singulis
— 1 FlexRay moduli (V2.1) usque ad 10 Mbit/s cum duali vel uno canali et 128 nuntius rerum et ECC.
• 1 eMIOS: 24 rivos unitos
• 1 eTPU2 (secunda generatio eTPU)
- XXXII vexillum canales
- I moduli reactionem (ex tribus outputs per channels VI channel)
• 2 aucta amet converters analog-ad-digitalis (eQADCs)
— Quadraginta 12-bit canales initus (multiplexus in 2 ADCs);expandable ad LVI vias exterioribus multiplicibus
- 6 imperium queues
- Trigger et DMA firmamentum
— 688 ns minimum conversionis tempus
• De-chip Can / SCI / FlexRay Bootstrap oneratus cum Tabernus adjuva amet (BAM)
• Nexus
- Classis 3+ pro e200z4 core
— Classis 1 pro eTPU
• JTAG (5-pin)
• Trigger Semaphore Development (DTS)
- Registrum semaphorum (32-bits) et identificatio mandare
- Used ut pars Urguet notitia acquisition protocol
- EVTO clavum adhibetur instrumentum ad communicandum cum externo
• Horologium generationis
- On-chip 4-40 MHz principalis oscillator .
- De chip FMPLL (frequency-modulata tempus-clausum loop)
• Ad CXX generali proposito I / O lineae
- Singillatim programmabiles ut initus, output vel munus speciale
- Limen Programmabile (hysteresis)
• Potentia modus reductionis: tardus, siste et sta-modis
• Flexibile rerum copia
— 5 V una copia cum exterioribus saburra
— Multiplex copia externa: 5 V, 3.3 V et 1.2 V .
• Packages
— 176 LQFP
— 208 MAPBGA
— 324 TEPBGA
496-pin CSP (calibration instrumentum tantum)
