STM32H743ZGT6 ARM Microcontrolers - MCU summus perficientur & DSP DP-FPU, Arm Cortex-M7 MCU 1MByte Flash 1MB RAM, 480 MH

Description:

Manufacturers: STMicroelectronics
Product Category: Microcontrollers 8-bit - MCU
Data Sheet:STM32H743ZGT6
Description: Microcontrollers - MCU
RoHS status: RoHS Compliant


Product Detail

Features

Product Tags

Product Description

Productum attributum Precium attributum
Fabrica: STMicroelectronics
Product Category: ARM Microcontrollers - MCU
RoHS: Singula
Series: STM32H7
Adscendens Style: SMD/SMT
Sarcina / Case: LQFP-144
Core: ARM Cortex M7
Programma Memoria Location: 1 MB
Data Bus Latitudo: 32 bit
ADC Consilium: 3 x 16 bit
Maximum Horologium Frequency: 480 MHz
Numerus I / Os: 114 I/O
Data Ram Size: 1 MB
Supple intentione - Min: 1.62 V
Supple intentione - Max: 3.6 V
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 85 C
Packaging: Tray
Notam: STMicroelectronics
DAC Resolutio: 12 bit
Data RAM Type: SRAM
I/O intentione: 1.62 V ad 3.6 V
Interface Type: CAN, Aer, LPUART, QSPI, SAI, SDMMC, SPI / I2S, UART / USART, USB
Humor Sensitivus: Ita
Numerus ADC canales: 36 Channel
Productum: MCU+FPU
Product Type: ARM Microcontrollers - MCU
Programma Memoria Type: Flash
Factory Pack Quantity: 360
Subcategoria: Microcontrollers - MCU
Nomen: STM32
Watchdog Timers: Watchdog Timer, Windowed
Unitas pondus: 0.09385 oz

 

♠ 32-bit Arm® Cortex®-M7 480MHz MCUs, usque ad 2MB Flash, usque ad 1MB RAM, 46 com.et Analog interfaces

STM32H742xI/G et STM32H743xI/G machinis innituntur summus perficientur Arm® Cortex®-M7 32-bit nucleus RISC operans usque ad 480 MHz.Cortex® -M7 nucleus notae fluctuationis punctum unitatis (FPU) quae Arm® praecisionem duplicem (IEEE 754 obsecundantem sustinet) et una subtilitas notitiarum processuum instructionum et datarum generum. STM32H742xI/G et STM32H743xI/G machinas plenam paroecialem sustinent. de DSP instructiones et unitas tutelae memoriae (MPU) ad securitatem applicationem augendae.

STM32H742xI/G et STM32H743xI/G cogitationes memoriae infixae cum duplicali ripa Mico memoriae incorporandi sunt, usque ad 2 Mbytes, usque ad 1 Mbyte RAM (including 192 Kbytes de TCM RAM, usque ad 864 Kbytes usoris SRAM et 4 Kbytes de tergum SRAM), tum amplis amplis I/Os et periphericis cum APB buses, AHB buses, 2x32-bit multi- bus matricis AHB et multi strati AXI inter se coniungunt aditum memoriam internam et externam sustinentes.


  • Previous:
  • Deinde:

  • Core

    • 32-bit Arm® Cortex®-M7 nucleus cum duplici praecisione FPU et L1 cache: 16 Kbytes notitiarum et 16 kbytes cella instructionis;frequentia usque ad 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), et instructiones DSP

    Memoriae

    • Ad II Mbytes de Flash memoriae cum legere-cum-scribere firmamentum

    • Usque ad 1 Mbyte de RAM: 192 Kbytes de TCM RAM (inc. 64 Kbytes de ITC RAM + 128 Kbytes de DTCM RAM tempore criticae consuetudines), Usque ad 864 Kbytes usoris SRAM, et 4 Kbytes de SRAM in Tergum domain

    • Dual modus Quad-SPI memoria interfaciei accurrit ad 133 MHz

    • Flexibile memoriae externae moderatoris usque ad 32 frenum data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NO/NAND Mico memoria clocked usque ad 100 MHz in modo Synchrono.

    • CRC unitas calculum

    Securitas

    • ROP, PC-ROP, activum sollicitare

    General-proposito initus/outputs

    • Usque ad CLXVIII I / O portus facultatem adjicias

    Reset et imperium procuratio

    • 3 ditiones potentiae separatae quae sine clock-gato vel switchedi esse possunt;

    - D1: summus perficientur capabilities

    - D2: communicationis peripherales et timers

    - D3: reset / horologium imperium / potentia procuratio

    • 1.62 ad 3.6 V applicationis copiam et I/Os

    • POR, PDR, PVD et BOR

    • USB potentiae dedicatae 3.3 V ordinator internus embedendi ad supplendam internam PHYs

    • Regulator Embedded (LDO) configurable scalable output supplere digitalis circuitry

    • intentione scalis in currendo et Sistere modus (configurable VI septa)

    • Tergum moderator (~0.9 V)

    • Voltage reference for Analog periphericum/VREF+

    • Low-power modes: Somnus, Siste, Standby et VBAT sustinentes altilium præcipientes

    Humilis potentia consummatio

    • VBAT altilium operandi modus cum præcipiens facultatem

    • CPU and domain power state vigilanting pins

    • 2.95 µA in Sto modo (Tergum SRAM OFF, RTC/LSE ON)

    Horologium procuratio

    • Oscillatores interni: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI.

    • Oscillatores externi: 4-48 MHz HSE, 32.768 kHz LSE

    • 3× PLLs (1 pro ratio horologii, 2 pro nucleo horologiorum) cum modo fracto

    Interconnect matrix

    • 3 bus matrices (1 AXI et 2 AHB)

    • Pontes (5× AHB2-APB, 2× AXI2-AHB)

    IV DMA moderatoris exonerare CPU

    • 1× summus celeritas dominus directus memoriae obvius moderatoris (MDMA) cum indice coniuncto auxilio

    • 2× dual-portus DMAs cum FIFO

    • 1× basic DMA cum iter itineris petitionem capabilities

    Ad XXXV communicationis peripherals

    • 4× I2Cs FM+ interfaces (SMBus/PMBus)

    • 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, usque ad 12.5 Mbit/s) et 1x LPUART.

    • 6× SPIs, 3 cum muxed duplex I2S accurationis genus audii per PLL internum seu externum horologium, 1x I2S in LP domain (usque ad 150 MHz)

    • 4x SAIs (Vide audio interface)

    • SPDIFRX interface

    • SWPMI unum filum protocol dominus I / F *

    • MDIO Servus interface

    • 2× SD/SDIO/MMC interfaces (usque ad 125 MHz)

    • 2× moderatores POTEST: 2 cum FD Can, 1 cum tempore Can (TT-CAN)

    • 2× USB OTG interfacies (1FS, 1HS/FS) cristallina solutionis minus cum LPM et BCD.

    • Aer MAC interface cum DMA controller

    • HDMI-CEC

    • 8- ad XIV-camera interface frenum (usque ad LXXX MHz)

    XI Analog peripherals

    • 3× ADCs cum 16-bit max.resolutio (usque ad XXXVI canales, ad 3.6 MSPS)

    • 1× temperatus sensorem

    • 2× 12-bit D/A conversis (1 MHz)

    • 2× ultra-humilis potentia comparatorum

    • 2× ampliatores perficiendi (Sed 7.3 MHz)

    • 1× Filtra digitalis pro sigma della modulator (DFSDM) cum canalibus 8/4 filters

    Graphics

    • LCD-TFT moderatoris ad XGA resolutio

    • Chrom-ART hardware graphical Accelerator (DMA2D) ad redigendum CPU onus

    • Hardware JPEG Codec

    Ad XXII timers et canes

    • 1× summus consultum timor (2.1 ns max resolutio)

    • 2× 32-bit timers usque ad 4 IC/OC/PWM vel pulsus calculo et quadratura (incrementalis) encoder initus (usque ad 240 MHz)

    • 2× 16-bit timers imperium motoris provectum (usque ad 240 MHz)

    • 10× 16-bit generalis propositi timers (usque ad 240 MHz)

    • 5× 16-bit potentia humilis timers (usque ad 240 MHz)

    • 2× canes (solutae et fenestrae)

    • 1× SysTick timer

    • RTC cum sub-secundo accurate et hardware calendarium

    Debug modus

    • SWD & JTAG interfaces

    • 4-Kbyte embedded Trace Buffer

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