STM8S207CBT6 8-bit Microcontrolers – euismod MCU Linea, 24 MHz STM8S 8-bit MCU
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | STMicroelectronics |
| Product Category: | 8-bit Microcontrollers - MCU |
| RoHS: | Singula |
| Series: | STM8S207CB |
| Adscendens Style: | SMD/SMT |
| Sarcina / Case: | LQFP-48 |
| Core: | STM8 |
| Programma Memoria Location: | 128 kB |
| Data Bus Latitudo: | 8 bit |
| ADC Consilium: | 10 bit |
| Maximum Horologium Frequency: | 24 MHz |
| Numerus I / Os: | 38 I/O |
| Data Ram Size: | 6 kB |
| Supple intentione - Min: | 2.95 V |
| Supple intentione - Max: | 5.5 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 85 C |
| Packaging: | Tray |
| Notam: | STMicroelectronics |
| Height: | 1.4 mm |
| Interface Type: | CAN, I2C, SPI, UART . |
| Longitudo; | 7 mm |
| Humor Sensitivus: | Ita |
| Numerus ADC canales: | 10 Channel |
| Numerus Timers / Calculis: | 6 Timer |
| Processus Series: | STM8S20x |
| Product Type: | 8-bit Microcontrollers - MCU |
| Programma Memoria Type: | EEPROM |
| Factory Pack Quantity: | 1500 |
| Subcategoria: | Microcontrollers - MCU |
| Latitudo: | 7 mm |
| Unitas pondus: | 0.00646 oz |
linea euismod, 24 MHz STM8S 8-bit MCU, usque ad 128 KB Flash, integratur EEPROM, 10 frenum ADC, timers, 2 UARTs, SPI, I²C, CAN.
StM8S20xxx perficientur linea 8-bit microcontrolers offerunt ab 32 ad 128 Kbytes programma memoriae programma.Referuntur ad cogitationes altae densitatis in STM8S microcontroller familias manuales referentes.
Omnes STM8S20xxx machinis sequentia beneficia praebent: systema reductum sumptus, robur perficiendi, cursus evolutionis breves et longitudinis producti.
Sumptus systematis gratiae integrae verae datae EEPROM reducitur ut usque ad 300 k cyclos scribe/raiones et systematis integrationis altam cum internis horologii oscillatoribus, vigilibus, et in reseti brunneo.
Fabrica perficiendi cavetur a 20 MIPS ad 24 MHz CPU horologii frequentiam et notas auctas quae includunt canes robusti I/O, canes independentes (cum fonte separato horologii), et systema securitatis horologii.
Brevis cycli progressus praestatur propter applicationem scalabilitatis per communem familiam producti architecturae cum pinout compatible, tabula memoriae et periphericis modulari.Plena documenta exhibetur cum ampla instrumentorum evolutionis electione.
Productum longitudinis vita conservatur in familia STM8S gratias ad nucleum provectum, qui factus est in technologia artis statu-of- applicationes cum 2.95 V ad 5.5 V operativarum copia.
■ Core
- Max fCPU: usque ad 24 MHz, 0 insidiae civitates @ fCPU ≤16 MHz
- Provectus STM8 core cum architectura Harvardiana et III scaena pipeline
- Extenso set disciplinam
- Max 20 MIPS @ 24 MHz
■ Memoriam
- Programma: usque ad 128 Kbytes Flash;data retentione XX annis apud LV ° C post X kcycles
– Data: usque ad 2 Kbytes data vera EEPROM;patientia CCC kcycles
- RAM: usque ad VI Kbytes
■ Horologium, reset et administratio praestabit
- 2.95 ad 5.5 V intentione operante
- Minimum potentia crystal resonator oscillator
- Horologium externum initus
- Internus, usor-tormabilis 16 MHz RC
- Interna vis humilis 128 kHz RC
- Pro securitatem ratio cum horologium monitor
– Exspecta, activa claude, et claude modos humilis potentia
- Periphericum horologiorum singulos switched off
- Permanenter activae, humilis consummatio in potestate et potestate, reset et descendit
■ Interpellare procuratio
- Nested adjicias moderatoris cum XXXII obloquitur
- Ad XXXVII extra obloquitur in VI vector
■ Timers
– 2x 16-bit generalis propositi timers, cum canalibus 2+3 CAPCOM (IC, OC vel PWM)
- Provectus imperium timoris: 16 frenum, 4 capcom canales, 3 outputationes complementarias, insertio temporis mortui et synchronisation flexibilis
- VIII-bit basic timor ad VIII-bit prescaler
- Auto expergiscimini timer
- Fenestra vigil, independens vigil
■ Communications interfaces
- High celeritate I Mbit / s beCAN 2.0B activae
- UART cum horologium output pro synchrono operatione - LIN dominus modus
- UART cum LIN 2.1 obsequiosus, dominus/servus modi et resynchronization latae
- SPI interface ad X Mbit / s *
- I2C interface ad CD Kbit / s *
■ 10-bit ADC cum usque ad 16 canales
■ I/Os
- Ad LXVIII I / Os in an LXXX-pin sarcina comprehendo XVIII altum submersa outputs '
- Valde robustum I/O consilium, contra vena iniectio immunis
- Development firmamentum
- Una filum interface moduli (NATO) et lusione moduli (DM)
■ 96-bit unique ID key for each device
