TMS320C6678ACYPA Multicore Fix/Float Pt Dig Sig Proc

Description:

Manufacturers: Texas Instrumenta
Product Category: Embedded - DSP (Digital signum Processors)
Data Sheet:TMS320C6678ACYPA
Description: IC DSP FIX/FLOAT proceditur 841FCBGA
RoHS status: RoHS Compliant


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Product Description

Productum attributum Precium attributum
Fabrica: Texas Instrumenta
Product Category: Digital Signum Processores & Moderatores - DSP, DSC
Productum: DSPs
Series: TMS320C6678
Adscendens Style: SMD/SMT
Sarcina / Case: FCBGA-841
Core: C66x
Numerus Cores: 8 Core
Maximum Horologium Frequency: 1 GHz, 1.25 GHz
L1 Cache Instructio Memoria: 8 x 32 kB
L1 Cache Data Memoria: 8 x 32 kB
Programma Memoria Location: -
Data Ram Size: -
Supple intentione operating: 900 mV ad 1.1 V
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 100 C
Packaging: Tray
Notam: Texas Instrumenta
Data Bus Latitudo: 8 bit/16 bit/32 bit
Instructio Type: Fixum / fluctuetur
MMACS: 320000 MMACS
Humor Sensitivus: Ita
Numerus I / Os: 16 I/O
Numerus Timers / Calculis: 16 Timer
Product Type: DSP - Digital signum Processors & Controllers
Factory Pack Quantity: 44
Subcategoria: Embedded Processors & Controllers
Supple intentione - Max: 1.1 V
Supple intentione - Min: 900 mV
Unitas pondus: 0.252724 oz

Multicore certa et fluctuetur-Point Digital signum Processor

TMS320C6678 DSP maxima opera fixa est / punctum DSP fluitantis quod ex architectura multicore TI in KeyStone fundatur.Incorporandi novum et innovative C66x DSP nucleum, haec fabrica currere potest ad nucleum celeritatis usque ad 1.4 GHz.In tincidunt amplis applicationibus, ut systemata missionali criticae, imaginatio edica, probatio et automatio, et aliae applicationes quae altam requirunt observantiam, TMS320C6678 DSP TI's 11.2 GHz cumulativum DSP offert et suggestum efficax et facile dat. uteris.Praeterea plene retrorsum compatible cum omni exsistente C6000 domo fixa et fluctuetur punctum DSPs.

TI'S KeyStone architectura praebet programmabilem suggestum variis subsystematibus (C66x coros, memoriae subsystem, periphericis et acceleratoribus) et utitur pluribus componentibus et technicis rationibus ad maximizandum intra-machinam et inter-machinam communicationis, quae varias facultates DSP efficienter et compagem operandi permittit. .Integrae huic architecturae partes praecipuae sunt ut Multicore Navigator qui dat procurationem efficientis inter varias machinas compositas.TeraNet est fabricae transiens non-obclusio ut motus celeritatis et contentionis liberorum internorum notitiarum possit.Multicore communis memoria moderatoris aditum ad memoriam communem et externam permittit directe sine e facultate switch fabricae trahens.


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  • Deinde:

  • • Octo TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Quisque cum
    – 1.0 GHz, 1.25 GHz, vel 1.4 GHz C66x Fixarum/Point CPU Core
    44.8 GMAC/Core ad certum punctum @ 1.4 GHz
    22.4 GFLOP/Core for Floating Point @ 1.4 GHz
    - Memoria
    › 32K Byte L1P Per Core
    32K Byte L1D Per Core
    › 512K Byte Local L2 Per Core
    • Multicore Shared Memoria Controller (MSMC)
    - 4096KB MSM SRAM Memoria Communes per octo DSP C66x CorePacs
    - Memoria Protectionis Unitas utriusque MSM SRAM et DDR3_EMIF
    • Multicore Navigator
    - 8192 Multipurpose Hardware Queues cum Queue Manager
    - fasciculum-Substructio DMA ad Nulla supra caput Transfers
    • Network Coprocessor
    - Packet Accelerator ope Support
    › Transporto Planum IPsec, GTP-U, SCTP, PDCP
    L2 User Planum PDCP (RoHC, Air Ciphering)
    ›1-Gbps Wire velocitate Throughput ad 1.5 MPackets Per Second
    - Securitatis Accelerator Engine ope adiuvat
    IPSec, SRTP, 3GPP, WiMAX Aeris mollis ac SSL/TLS Securitatis
    › ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, NIVEUS 3G, SHA-1, SHA-2 (256-bit Hash), MD5
    Ad 2.8 Gbps Encryption Volo
    • Peripherals
    - Quattuor vicos SRIO 2.1
    1.24/2.5/3.125/5 Operatio GBaud suffulta Per Lane
    subsidia Direct I/O, Nuntius Transitus
    Sustinet quattuor 1×, duae 2×, unus 4×, et duae 1× + unus 2×, Link configurationes
    – Plu Gen2
    Unius Portus Supportantes I vel II Lancs
    Sustinet ad V GBaud Per Lane
    - HyperLink
    subsidia connexiones ad Alia KeyStone Architectura machinae Providentes Resource Scalability
    subsidia ad L Gbaud
    – Gigabit Ethernet (GbE) Switch Subsystem
    Duo SGMII portuum
    subsidia 10/100/1000 Mbps Operatio
    - 64-Bit DDR3 Interface (DDR3-1600)
    8G MB Addressable Memoria Space
    - 16-bit EMIF
    - Duo Telecom Serial Portus (TSIP)
    subsidia 1024 DS0s Per TSIP
    Supports 2/4/8 Lancs at 32.768/16.384/8.192 Mbps Per Lane
    - UART Interface
    - I2
    C Interface
    - 16 GPIO Pins
    - SPI Interface
    - Semaphore amet
    - Sedecim 64-bit Timers
    - Tres De Chip PLLs
    • Commercial Temperature:
    - 0°C ad 85°C
    • Calor Extensus:
    – -40°C ad 100°C

    • Mission-Critical Systems
    • High-Perficiendi Computing Systems
    • Communications
    • Audio
    • Vide Infrastructure
    • Imaging
    • Analytics
    • Networking
    • Media Processing
    • Industrial Automation
    • Automation et Processus Imperium

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