TMS320F2812PGFA Digital signum Processors ac moderatoris DSP DSC 32Bit Digital Sig Controller w/Flash

• summus perficientur CMOS technologiae stabilis
- 150 MHz (6.67-ns cycli temporis)
– Vis Belgica (1.8-V core in 135 MHz;1.9-V core apud 150 MHz, 3.3-VI/O) design

• JTAG terminus scan firmamentum
- IEEE Standard 1149.1-1990 IEEE StandardTest Access Portus et terminus ScanArchitecture

• Summus perficientur 32-bit CPU (TMS320C28x)
16 16 et 32 ​​32 MAC operationes
- 16 16 dual MAC
- Harvard bus architectura
- Operationes atomicae
- Fast responsio adjicias et dispensando
- Programming exemplar memoriae Unified
- 4M linearibus programma / data electronica semoto
- Codex efficens (in C/C ++ et Conventus)
- TMS320F24x/LF240x processus source codecompatible

• De memoria-chip
- Ad 128K XVI mico(quattuor 8K 16 et sex 16K × 16 partes)
– 1K 16 OTP ROM
- L0 et L1: 2 cuneos 4K XVI singulis SingleAccess RAM (SARAM)
– H0: 1 scandalum 8K 16 SARAM
- M0 et M1: 2 cuneos 1K 16 inter SARAM

• Boot ROM (4K 16)
- Cum software tabernus modos
- Latin math tables

• Interface (F2812)
- Per 1M XVI totalis memoria
- Programmable insidias civitatibus
- Programmable legere / scribere strobe leo
- Tres singula chip eligit

• Endianness: Parva endian

• Pro et ratio imperium
- De-chip oscillator
- Watchdog timor moduli

• Tres externa obloquitur

• Periphericum Interrumpere Expansion (PIE) angustos thatsustinet XLV periphericis obloquitur

• Tres 32-bit CPU timers

• CXXVIII-bit securitatis clavis / cincinno
- mico protegit / OTP et L0 / L1 SARAM
- Prevents firmware vicissim ipsum

• Motor imperium peripherals
- Duo Event administratores (EVA, EVB)
- Compatible ad 240xA cogitationes

• Vide portum peripherals
- Serial interface periphericis (SPI)
- Duo interfaces Serial Communications (SCIs);vexillum UART
- Area Network Consectetur Controller (eCAN)
- Multichannel Buffered Serial Portus (McBSP)

• 12 frenum ADC, 16 canales
- 2 8 channel input multiplexer
- Duo Sample et habe
- Singulus / simul conversiones
- Fast conversionem rate: 80 ns/12.5 MSPS

• Ad 56 General-Propositum I/O (GPIO) fibulae

• Advanced features aemulatio
- Analysis et breakpoint munera
- Real-time debug per hardware

• instrumenta progressio includit
- ANSI C/C++ compilator/congregator/linker
- Code Composer Studio™ IDE
- DSP/BIOS™
- JTAG scan moderatoris

• IEEE Standard 1149.1-1990 IEEE StandardTest Access Portus et terminus ScanArchitecture

• Low-potentiae modos et potentiam peculi
- VACE, sto, claude modorum sustentatur
- inactivare singula periphericis horologiorum

• Package optiones
- 179-pila MicroStar BGA™ cum externa memoriainterface (GHH, ZHH) (F2812)
- 176-pin Low-Profile Quad Flatpack (LQFP) withMemoria externa instrumenti (PGF) (F2812)
- 128-pin LQFP sine memoria externainterface (PBK) (F2810, F2811)

• Temperature optiones
– A: -40°C ad 85°C (GHH, ZHH, PGF, PBK)
– S: -40°C ad 125°C (GHH, ZHH, PGF, PBK)
– Q: -40°C ad 125°C (PGF, PBK)(AEC-Q100 absolute pro autocineto
applications)

• Provectus Coegi auxilium Systems (ADAS)

• Aedificium automation

• punctum venditionis Electronic

• Vehiculum Electric / Hybrid Vehiculum Electric (EV/HEV)powertrain

• Factory automation

• eget infrastructure

• onerariam Industrial

• Medical, curis, et idoneitate

• motor agit

• Power partus

• Telecom infrastructure

• Test et mensura