PIC18F26K83-I/SS 8bit Microcontrollers MCU 12BIT ADC2 64KB Flash 4KB RAM
Product Description
| Productum attributum | Precium attributum |
| Fabrica: | Microchip |
| Product Category: | 8-bit Microcontrollers - MCU |
| RoHS: | Singula |
| Series: | PIC18(L)F2xK83 |
| Adscendens Style: | SMD/SMT |
| Sarcina / Case: | SSOP-28 |
| Core: | PIC18 |
| Programma Memoria Location: | 64 kB |
| Data Bus Latitudo: | 8 bit |
| ADC Consilium: | 12 bit |
| Maximum Horologium Frequency: | 64 MHz |
| Numerus I / Os: | 25 I/O |
| Data Ram Size: | 4 kB |
| Supple intentione - Min: | 2.3 V |
| Supple intentione - Max: | 5.5 V |
| Minimum Operating Temperature: | - 40 C |
| Maximum Operating Temperature: | + 85 C |
| Packaging: | Tubus |
| Notam: | Microchip Technology / Atmel |
| DAC Resolutio: | 5 bit |
| Data RAM Type: | SRAM |
| Data ROM Size: | 1024 B |
| Data ROM Type: | EEPROM |
| Interface Type: | CAN, I2C, LIN, SPI, UART . |
| Humor Sensitivus: | Ita |
| Numerus ADC canales: | 24 Channel |
| Productum: | MCU |
| Product Type: | 8-bit Microcontrollers - MCU |
| Programma Memoria Type: | Flash |
| Factory Pack Quantity: | 47 |
| Subcategoria: | Microcontrollers - MCU |
| Nomen: | PIC |
| Watchdog Timers: | Watchdog Timer, Windowed |
| Unitas pondus: | 0.02341 oz |
28-pin, Low-Power, High-Perficiendi Microcontrollers cum Can Technology
PIC18(L)FXXK83 est plena Featured POTEST familia producta quae in applicationibus autocinetis et industrialibus adhiberi potest.Multitudo communicationis periphericorum in familia producta inventa est, ut CAN, SPI, duo I2Cs, duo UARTs, LIN, DMX et DALI amplis instrumentorum communicationis instrumentorum communicationis protocolla ad applicationes intelligendas tractare possunt.Familia haec duodecim frenum ADC includit cum extensionibus computationis (ADC2) pro analysi automated signo ad implicationem applicationis reducendam.Haec, cum Core Independentium facultates integrationes Peripherales coniunctae, functiones praebet ad imperium motorum, copiam potentiarum, sensorem, signum et applicationes interfaciei usoris.
• C Compiler Optimised RISC Architecture
• operating velocitate
- Ad LXIV MHz horologium operandi
- 62.5 ns cyclum minimum instructionis
• Duo Direct Memoria Access (DMA) Moderatores:
- Data translationes ad SFR/GPR spatia asive Programma Mico Memoria, DataEEPROM vel SFR / GPR spatia
- User-programma principium et destinationemmagnitudinum
- Hardware et programmatibus Urguet datatransfert
• Ratio bus Arbiter cum User-configurablePriores de Scanner et DMA1/DMA2 withrespicit acie interrumpere supplicium
• Vectored Facultatem adjicias:
- Selectable alta / prius humilis
- certa adjicias latency
- Programmable vector mensam base inscriptio
• 31-Level Deep Hardware Stack
• Low-Current Power-de Reddere (POR)
• Configurable Power-sursum Vicis (PWRT)
• Brown-Ex Reddere (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT);
- Variabilis precator lectio
- Variabilis fenestrae magnitudo lectio
- Configurable in hardware vel software
